A conventional multiplexer for selecting four bits out of 16 bits is shown schematically in FIG. 1. Each of the subsections 131-134 of the four bit register 130 is connected by lines 140, 150 to each of the subsections 111-126 of the sixteen bit register 110. For clarity on the figure, only those lines 140 which connect subsection 131 of the four bit register 130 to each of the subsections 111-126 of the sixteen bit register 110 and those lines 150 which connect the subsection 126 of the sixteen bit register 110 to each of the subsections 131-134 of the four bit register 130 are shown. In an actual implementation, however, each of the subsections 111-126 of the sixteen bit register 110 would have four outputs, each going to one of the subsections 131-134 of the four bit register 130, and each of the subsections 131-134 of the four bit register 130 will have sixteen inputs, each coming from one of the subsections 111-126 of the sixteen bit register 110. On FIG. 1, one line, that connecting subsection 126 of the sixteen bit register 110 with subsection 131 of the four bit register 130, is shown as being part of both groups of lines 140, 150.
The logical implementation of part of this structure is shown in FIG. 2. Each of the subsections 111-126 of the sixteen bit register 110 is connected to a first input of one of the AND gates 161-176. The second input to the AND gates 161-176 is from a multiplexer controller (not shown). The outputs of the AND gates 161-164 are connected to the inputs of the four input OR gate 181. The outputs of the AND gates 165-168 are connected to the inputs of the four input OR gate 182. The outputs of the AND gates 169-172 are connected to the inputs of the four input OR gate 183. The outputs of the AND gates 173-176 are connected to the inputs of the four input OR gate 184. Each of the outputs of the OR gates 181-184 are connected to a different one of the inputs of the four input OR gate 185. The output 160 of the OR gate 185 is connected to the input of one of the subsections 131-134 of the four bit register 130. The whole circuit of FIG. 2 is repeated four times in the multiplexer as each of outputs 160 is connected to only one of the subsections 131-134 of the four bit register 130. If it is then desired to transfer one of the bit values from one of the subsections 111-126 of the sixteen bit register 110 to one of the subsections 131-134 of the four bit register 130, then a high signal is placed by the multiplexer controller on the second input of the corresponding AND gate 161-176 and the desired bit value appears at the output 160 from whence it can be passed into the one of the subsections 131-134 of the four bit register 130 to which the multiplexer is connected.
This design has the disadvantage in that it contains a large amount of redundant wiring and logic gates. For example, each of subsections 111-126 of the sixteen bit register 110 can be connected through the appropriate logic gates to all of the subsections 131-134 of the four bit register 130 even though; in some applications, the value of the bit in a subsection 111-126 of the sixteen bit register 110 will be passed to only one of the subsections 131-134 of the four bit register 130. The effect of this redundant wiring is to slow down the operation of the multiplexer as the lines are longer than they need to be and there is a surplus load on the each of the subsections 111-126 of the sixteen bit register 110. In addition, the redundant logic gates use a great deal of space on the chip which could be better employed.